A fault-tolerant sequential circuit design for stuck-at faults and path delay faults A. Y. Matrosova, S. A. Ostanin, I. E. Kirienko [et.al.]
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ArticleOther title: Проектирование отказоустойчивых последовательностных схем для константных неисправностей и неисправностей задержек путей [Parallel title]Subject(s): отказоустойчивые схемы | последовательностные схемы | самопроверяемые схемы | константные неисправности | неисправности задержек путей | нерегулярные ошибкиGenre/Form: статьи в журналах Online resources: Click here to access online
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Вестник Томского государственного университета. Управление, вычислительная техника и информатика № 41. С. 61-68Abstract: This paper presents a fault-tolerant synchronous sequential circuit design based on self-checking system with low overhead. The scheme has only one self-checking sequential circuit, normal (unprotected) sequential circuit and not selftesting checker. It is proved the reliability properties of the suggested scheme both for single stuck-at faults (SAFs) at gate poles and path delay faults (PDFs), transient and intermittent. It is supposed that each next fault appears when a previous one has disappeared. Estimations of the schemes complexity are discussed.
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This paper presents a fault-tolerant synchronous sequential circuit design based on self-checking system with low overhead. The scheme has only one self-checking sequential circuit, normal (unprotected) sequential circuit and not selftesting checker. It is proved the reliability properties of the suggested scheme both for single stuck-at faults (SAFs) at gate poles and path delay faults (PDFs), transient and intermittent. It is supposed that each next fault appears when a previous one has disappeared. Estimations of the schemes complexity are discussed.
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