Detection and masking of Trojan Circuits in sequential logic A. Y. Matrosova, E. V. Mitrofanov, S. A. Ostanin, E. A. Nikolaeva
Material type:
ArticleSubject(s): последовательная логика | последовательностные схемы | ROBDD-графы | вредоносные подсхемыGenre/Form: статьи в сборниках Online resources: Click here to access online
In:
Proceedings of 2017 IEEE East-West Design & Test Symposium (EWDTS), Novi Sad, Serbia, September 27 – October 2, 2017 P. 137-140Abstract: A technique of finding a set of sequential circuit
nodes in which Trojan Circuits (TC) may be implanted
is suggested. The technique is based on applying the
precise (not heuristic) random estimations of internal
node observability and controllability. Getting the
estimations we at the same time derive and compactly
represent all sequential circuit full states (depending
on input and state variables) in which of that TC may
be switched on. It means we obtain precise description
of TC switch on area for the corresponding internal
node v. The estimations are computed with applying a
State Transition Graph (STG) description, if we
suppose that TC may be inserted out of the working
area (out of the specification) of the sequential circuit.
Reduced Ordered Binary Decision Diagrams
(ROBDDs) for the combinational part and its
fragments are applied for getting the estimations by
means of operations on ROBDDs. Techniques of
masking TCs are proposed. Masking sub-circuits
overhead is appreciated.
Библиогр.: 9 назв.
A technique of finding a set of sequential circuit
nodes in which Trojan Circuits (TC) may be implanted
is suggested. The technique is based on applying the
precise (not heuristic) random estimations of internal
node observability and controllability. Getting the
estimations we at the same time derive and compactly
represent all sequential circuit full states (depending
on input and state variables) in which of that TC may
be switched on. It means we obtain precise description
of TC switch on area for the corresponding internal
node v. The estimations are computed with applying a
State Transition Graph (STG) description, if we
suppose that TC may be inserted out of the working
area (out of the specification) of the sequential circuit.
Reduced Ordered Binary Decision Diagrams
(ROBDDs) for the combinational part and its
fragments are applied for getting the estimations by
means of operations on ROBDDs. Techniques of
masking TCs are proposed. Masking sub-circuits
overhead is appreciated.
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