Testing digital circuits: studying the increment of the number of states and estimating the fault coverage E. Vinarskii, A. Laputenko, J. López, N. G. Kushik
Material type:
ArticleSubject(s): конечные автоматы | тестирование цифровых схем | цмфровые схемыGenre/Form: статьи в сборниках Online resources: Click here to access online
In:
19th International Conference of Young Specialists on Micro/Nanotechnologies and Electron Devices (EDM 2018), Erlagol, Altai Republic, 29 June - 3 July, 2018 : proceedings P. 220-224Abstract: Testing of digital circuits is very important,
especially for guaranteeing the correct and reliable
functioning of electronic devices. One of the possibilities for
deriving high quality test suites is using test generation
methods for a corresponding Finite State Machine simulating
the circuit behavior. In this paper, we estimate the number of
implementation states whenever a circuit mutant is
introduced. Experimental evaluation is performed for three
types of mutants, namely Single Stuck-At Fault Mutants,
Single Bridge Fault Mutants, and Hardly Detectable Fault
Mutants. Experiments with the ITC’99 benchmarks (second
release) show that in most cases the injection of a fault does
not increase the number of states. Moreover, whenever the
number of states is increased, the increment is on average
20%. Given this increment, we perform the experiments to
showcase that for testing circuits with guaranteed fault
coverage with respect to the listed faults, one can apply the Wmethod
with the upper bound m = 1.2n states, for n states in
the specification (circuit) FSM.
Библиогр.: 11 назв.
Testing of digital circuits is very important,
especially for guaranteeing the correct and reliable
functioning of electronic devices. One of the possibilities for
deriving high quality test suites is using test generation
methods for a corresponding Finite State Machine simulating
the circuit behavior. In this paper, we estimate the number of
implementation states whenever a circuit mutant is
introduced. Experimental evaluation is performed for three
types of mutants, namely Single Stuck-At Fault Mutants,
Single Bridge Fault Mutants, and Hardly Detectable Fault
Mutants. Experiments with the ITC’99 benchmarks (second
release) show that in most cases the injection of a fault does
not increase the number of states. Moreover, whenever the
number of states is increased, the increment is on average
20%. Given this increment, we perform the experiments to
showcase that for testing circuits with guaranteed fault
coverage with respect to the listed faults, one can apply the Wmethod
with the upper bound m = 1.2n states, for n states in
the specification (circuit) FSM.
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