Embedded Memory Design for Multi-Core and Systems on Chip electronic resource by Baker Mohammad.
Material type: TextSeries: Analog Circuits and Signal ProcessingPublication details: New York, NY : Springer New York : Imprint: Springer, 2014Description: XIII, 95 p. 63 illus., 37 illus. in color. online resourceContent type: text Media type: computer Carrier type: online resourceISBN: 9781461488811Subject(s): engineering | Computer Science | electronics | Systems engineering | Engineering | Circuits and Systems | Electronics and Microelectronics, Instrumentation | Processor ArchitecturesDDC classification: 621.3815 LOC classification: TK7888.4Online resources: Click here to access onlineIntroduction -- Cache Architecture and Main Blocks -- Embedded Memory Hierarchy -- SRAM Memory Operation and Yield -- Low Power and High Yield SRAM Memory -- Leakage Reduction -- Embedded Memory Verification -- Embedded Memory Design Validation and Design For Test -- Emerging Memory Technology Opportunities and Challenges.
This book describes the various tradeoffs systems designers face when designing embedded memory. Readers designing multi-core systems and systems on chip will benefit from the discussion of different topics from memory architecture, array organization, circuit design techniques and design for test. The presentation enables a multi-disciplinary approach to chip design, which bridges the gap between the architecture level and circuit level, in order to address yield, reliability and power-related issues for embedded memory. · Provides a comprehensive overview of embedded memory design and associated challenges and choices; · Explains tradeoffs and dependencies across different disciplines involved with multi-core and system on chip memory design; · Includes detailed discussion of memory hierarchy and its impact on energy and performance; · Uses real product examples to demonstrate embedded memory design flow from architecture, to circuit design, design for test and yield analysis.
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