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Simplification of fully delay testable combinational circuits and finding of pdf test pairs A. Yu. Matrosova, E. V. Mitrofanov, T. Shah

By: Matrosova, Anzhela YuContributor(s): Mitrofanov, Evgenii V | Shah, ToralMaterial type: ArticleArticleOther title: Упрощение контролепригодных комбинационных схем и поиск тестовых пар для неисправностей задержек путей [Parallel title]Subject(s): неисправности задержек путей | ROBDD-графы | контролепригодный синтезGenre/Form: статьи в журналах Online resources: Click here to access online In: Вестник Томского государственного университета. Управление, вычислительная техника и информатика № 39. P. 85-93Abstract: Fully delay testable circuits obtained by covering ROBDD nodes with Invert-AND-OR sub-circuits and Invert-ANDXOR sub-circuits implementing Shannon decomposition formula are considered. Algorithms of finding test pairs for robust testable PDFs and validatable non robust testable PDFs of resulted circuits have been developed. Experimental results demonstrate essential simplification of suggested circuits in contrast to fully delay testable circuits obtained by covering each ROBDD node with only Invert-AND-XOR sub-circuit.
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Fully delay testable circuits obtained by covering ROBDD nodes with Invert-AND-OR sub-circuits and Invert-ANDXOR sub-circuits implementing Shannon decomposition formula are considered. Algorithms of finding test pairs for robust testable PDFs and validatable non robust testable PDFs of resulted circuits have been developed. Experimental results demonstrate essential simplification of suggested circuits in contrast to fully delay testable circuits obtained by covering each ROBDD node with only Invert-AND-XOR sub-circuit.

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